M H C - 2 0 4 0 A T H O R N E T 9 FUJITSU Native| Translation ------+-----+-----+----- Form 2.5"/SUPERSLIMLINE Cylinders 7229| | | Capacity form/unform 4090/ MB Heads 6| | | Seek time / track 13.0/ 2.5 ms Sector/track | | | Controller IDE / ATA3 ULTRA Precompensation Cache/Buffer 512 KB Landing Zone Data transfer rate MB/S int Bytes/Sector 512 33.300 MB/S ext Recording method EPR4ML operating | non-operating -------------+-------------- Supply voltage 5 V Temperature *C 5 55 | -40 65 Power: sleep 0.1 W Humidity % 8 90 | 5 95 standby 0.4 W Altitude km -0.300 3.000| -0.300 12.000 idle 0.9 W Shock g 100 | 500 seek 2.4 W Rotation RPM 4000 read/write W Acoustic dBA 30 spin-up W ECC Bit SMART MTBF h 300000 Warranty Month Lift/Lock/Park YES Certificates
FUJITSU MHD-2021/2032AT/MHC2040AT JUMPER SETTING
+-------------------------------------------------------------+ | | | | | +-----------------------------------------------C-A-+ | | | * * * * * * * * * * * * * * * * * * * * * 1 * * | | | | * * * * * * * * * * * * * * * * * * * * * * * | | +----+----------------------------------------------SWITCH----+ D B
FUJITSU MHD-2021AT/2032AT/MHC2040AT JUMPER SETTING
+-------------------------------------------------------------+ | | | | | +---------------------------------------------------+ | | | * * * * * * * * * * * * * * * * * * * * * 1 * * | | | | * * * * * * * * * * * * * * * * * * * * * * * | | +----+----------------------------------------------SWITCH----+
Factory Default --------------- --------C-A-+ * * * | OPEN * * * * | ------D-B-+
MASTER-device * * * | * * * * | ----------+ Master drive (device #0) or slave (device #1) is SLAVE-device+ selected. * * * | * * xxx | Note: ----------+ Pins A and C should be open.
-CSEL-------+ * xxx |CSEL signal is enabled. * * * * | ----------+ NOTE The CSEL setting is not depended on setting between pins B and D.
By connecting the CSEL of the master device to the CSEL Line
(conductor) of the cable and connecting it to ground further, the
CSEL is set to low level.
The device is identified as a master device. At this time, the CSEL
of the slave device does not have a conductor. Thus, since the
slave device is not connected to the CSEL conductor, the CSEL is set
to high level. The device is identified as a slave device.
FUJITSU MHC-2032AT/2040AT PRODUCT MANUAL
Notes on installation
horizontally vertically +-----------------+ +--+ +--+ | | | +-----+ +-----+ | | | | | | | | | +-+-----------------+-+ | | | | | | +---------------------+ | | | | | | | | | | | | | | | | | | +---------------------+ | +-----+ +-----+ | +-+-----------------+-+ +--+ +--+ | | | | +-----------------+
The drive will operate in all axis (6 directions).
Power save mode
The power save mode feature for idle operation, stand by and sleep
modes makes the disk drive ideal for applications where power
consumption is a factor.
Wide temperature range
The disk drive can be used over a wide temperature range (5*C to
Low noise and vibration
In Ready status, the noise of the disk drive is only about 30 dBA
(measured at 1 m apart from the drive under the idle mode).
Connection to interface
With the built-in ATA interface controller, the disk drive can be
connected to an ATA interface of a personal computer.
512-KB data buffer
The disk drive uses a 512-KB data buffer to transfer data between the
host and the disk media.
In combination with the read-ahead cache system and the write cache,
the buffer contributes to efficient I/O processing.
Read-ahead cache system
After the execution of a disk read command, the disk drive
automatically reads the subsequent data block and writes it to the
data buffer (read ahead operation). This cache system enables fast
data access. The next disk read command would normally cause another
disk access. But, if the read ahead data corresponds to the
data requested by the next read command, the data in the buffer can
be transferred instead.
When the disk drive receives a write command, the disk drive posts
the command completion at completion of transferring data to the data
buffer completion of writing to the disk media. This feature reduces
the access time at writing.
The MR head bias of the HDD disk enclosure (DE) is zero. The mounting
frame is connected to SG.
Use M3 screw for the mounting screw and the screw length should
satisfy the specifications.
The tightening torque must not exceed 3 kgcm.
When attaching the HDD to the system frame, do not allow the
system frame to touch parts (cover and base) other than parts to
which the HDD is attached.
The temperature conditions for a disk drive mounted in a cabinet
refer to the ambient temperature at a point 3 cm from the disk drive.
The ambient temperature must satisfy the temperature conditions.
And the airflow must be considered to prevent the DE surface
temperature from exceeding 60*C.
Provide air circulation in the cabinet such that the PCA side, in
particular, receives sufficient cooling. To check the cooling
efficiency, measure the surface temperatures of the DE. Regardless of
the ambient temperature, this surface temperature must meet the
Data corruption: Avoid mounting the disk drive near strong
magnetic sources such as loud speakers. Ensure that the disk drive
is not affected by external magnetic fields.
Cable connector specifications
Name Model Manufacturer
Cable socket (44-pin type) 89361-144 BERG
Cable (44-pin type) FV08-A440 Junkosha
ATA interface and power supply cable (44-pin type)
For the host interface cable, use a ribbon cable. A twisted cable or
a cable with wires that have become separated from the ribbon may
cause crosstalk between signal lines. This is because the interface
is designed for ribbon cables and not for cables carrying
The CSEL setting is not depended on setting between pins Band D.
By connecting the CSEL of the master device to the CSEL Line
(conducer) of the cable and connecting it to ground further, the CSEL
is set to low level. The device is identified as a master device. At
this time, the CSEL of the slave device does not have a conductor.
Thus, since the slave device is not connected to the CSEL conductor,
the CSEL is set to high level. The device is identified as a slave
The DE contains disks with an outer diameter of 65 mm and an inner
diameter of 20 mm. The MHC2040AT has three disks and MHC2032AT has
The head contacts the disk each time the disk rotation stops; the
life of the disk is 50,000 contacts or more. Servo data is recorded
on top disk.
Servo data is recorded on each cylinder (total 54). Servo data
written at factory is read out by the read/write head.
MHA2032AT has 5 read/write heads and MHC2040AT has 6 read/write
heads. These heads are raised from the disk surface as the spindle
motor the rated rotation speed.
The spindle consists of a disk stack assembly and spindle motor. The
disk stack assembly is activated by the direct drive sensor-less DC
spindle motor, which has a speed of 4,000 rpm. The spindle is
controlled with detecting a PHASE signal generated by counter
electromotive voltage of the spindle motor at starting.
The actuator consists of a voice coil motor (VCM) and a head
carriage. The VCM moves the head carriage along the inner or outer
edge of the disk. The head carriage position is controlled by feeding
back the difference of the target position that is detected and
reproduced from the servo information read by the read/write head.
There are two types of air filters: a breather filter and a
The breather filter makes an air in and out of the DE to prevent
unnecessary pressure around the spindle when the disk starts or stops
rotating. When disk drives are transported under conditions where the
air pressure changes a lot, filtered air is circulated in the DE.
The circulation filter cleans out dust and dirt from inside the DE.
The disk drive cycles air continuously through the circulation filter
through an enclosed loop air cycle system operated by a blower on the
Power-on Sequence ----------------- a) After the power is turned on, the disk drive executes the MPU bus test, internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.
b) The disk drive executes self-diagnosis (data buffer read/write test) after enabling response to the ATA bus.
c) After confirming that the spindle motor has reached rated speed, the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM. This unlocks the heads which are parked at the inner circumference of the disks.
d) The disk drive positions the heads onto the SA area and reads out the system information.
e) The disk drive executes self-seek-calibration. This collects data for VCM tarque and mechanical external forces applied to the actuator, and updates the calibrating value.
f) The drive becomes ready. The host can issue commands.
Data transfer phase ------------------- a) The Data transfer phase is defined as the period from The Ultra DMA burst initiation phase to Ultra DMA burst termination phase.
b) The receiving side stops the Ultra DMA burst temporarily by negating DMARDY-signal, and then restarts the Ultra DMA burst by asserting again.
c) The transmitting side stops the Ultra DMA burst temporarily by not-performing inversion of STROBE signal, and then restarts the Ultra DMA burst by restarting the inversion.
d) When the transmitting side has stopped the inversion of STROBE signal, the receiving side should not output termination request signal immediately.
The receiving side should negate DMARDY signal when no termination request signal has been received from the transmission side, and then should output the termination request signal when a certain wait time has elapsed.
e) The transmitting side is allowed to send STROBE signal at a transfer speed that is lower than the one in the transferable fastest Ultra DMA mode, but is not allowed to send the STROBE signal at a higher speed than this. The receiving side should be able to receive the data in the transferable fastest Ultra DMA mode.
The write cache function of the drive makes a high speed processing
in the case that data to be written by a write command is physically
sequent the data of previous command and random write operation is
When the drive receives a write command, the drive starts
transferring data of sectors requested by the host system and writing
on the disk medium. After transferring data of sectors requested by
the host system, the drive generates the interrupt of command
complete. Also, the drive sets the normal end status in the Status
The drive continues writing data on the disk medium. When all data
requested by the host are written on the disk medium, actual write
operation is completed.
The drive receives the next command continuously. If the received
command is a "sequential write" (data to be written by a command is
physically sequent to data of previous command), the drive starts
data transfer and receives data of sectors requested by the host
system. At this time, if the write operation of the previous
command is still been executed, the drive continuously executes the
write operation of the next command from the sector next to the last
sector of the previous write operation. Thus, the latency time for
detecting a target sector of the next command is eliminated. This
shortens the access time.
The drive generates an interrupt of command complete after completion
of data transfer requested by the host system as same as at previous
When the write operation of the previous command had been completed,
the latency time occurs to search the target sector.
If the received command is not a "sequential write", the drive
receives data of sectors requested by the host system as same as
"sequential write". The drive generates the interrupt of command
complete after completion of data transfer requested by the host
system. Received data is processed after completion of the write
operation to the disk medium of the previous command.
Even if a hard reset or soft reset is received or the write cache
function is disabled by the SET FEATURES command during unwritten
data is kept, the instruction is not enabled until remaining
unwritten data is written onto the disk medium.
The drive uses a cache data of the last write command as a read cache
data. When a read command is issued to the same address after the
write command (cache hit), the read operation to the disk medium is
If an error occurs during the write operation, the device retries the
processing. If the error cannot be recovered by retry, automatic
alternate assignment is performed.
When Write Cache is permitted, the writing of the data transferred
from the host by the abovementioned Write Cache permit command
into the disk medium may not be completed at the moment a normal
ending interrupt has occurred.
In case a non-recoverable error has occurred during receiving more
than one write command, it is difficult for the host to identify a
command that caused the error.
(However, the error is not reported to the hose if an error at
writing has been processed normally.) Therefore, note that it is
difficult for the host to retry an operation that caused a non-
FUJITSU MHC-2032AT/2040AT PRODUCT MANUAL
Functions and performance ------------------------- - Compact The disk has 3 disks of 65 mm (2.5 inches) diameter, and its height is 12.5 mm (0.492 inch).
- Large capacity The disk drive can record up to 1,083 MB (formatted) on one disk using the (16/17) EPR4ML recording method and 13 recording zone technology. The MHC2032AT and MHC2040AT have a formatted capacity of 3.25 GB and 4.09 GB respectively.
- High-speed Transfer rate The disk drive has an internal data rate up to 9.8 MB/s. The disk drive supports an external data rate up to 33.3 MB/s (U-DMA).
- Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 13 ms (at read).
Mean time between failures (MTBF)
The mean time between failures (MTBF) is 300,000 H or more
(operation: 24 hours/day, 7 days/week).
This does not include failures occurring during the first three
months after installation.
MTBF is defined as follows:
Total operation time in all fields
MTBF= (H) number of device failure in all fields
"Disk drive defects" refers to defects that involve repair,
readjustment, or replacement. Disk drive defects do not include
failures caused by external factors, such as damage caused by
handling, inappropriate operating environments, defects in the power
supply host system, or interface cable.
Mean time to repair
(MTTR) The mean time to repair (MTTR) is 30 minutes or less, if
repaired by a specialist maintenance staff member.
In situations where management and handling are correct, the disk
drive requires no overhaul for five years when the DE surface
temperature is less than 48*C.
When the DE surface temperature exceeds 48*C, the disk drives
requires no overhaul for five years or 20,000 hours of operation,
whichever occurs first.
Data assurance in the event of power failure
Except for the data block being written to, the data on the disk
media is assured in the event of any power supply abnormalities. This
does not include power supply abnormalities during disk media
initialization (formatting) or processing of defects (alternative
Known defects, for which alternative blocks can be assigned, are not
included in the error rate count below. It is assumed that the data
blocks to be accessed are evenly distributed on the disk media.
Unrecoverable read error
Read errors that cannot be recovered by maximum 252 times read
retries without user's retry and ECC corrections shall occur no more
than 10 times when reading data of 10(14) bits. Read retries are
executed according to the disk drive's error recovery procedure, and
include read retries accompanying head offset operations.
Positioning (seek) errors that can be recovered by one retry shall
occur no more than 10 times in 10(7) seek operations.
Defective sectors are replaced with alternates when the disk is
formatted prior to shipment from the factory (low level format).
Thus, the host sees a defect-free device.
Alternate sectors are automatically accessed by the disk drive. The
user need not be concerned with access to alternate sectors.
HA (host adaptor) consists of address decoder, driver, and receiver.
ATA is an abbreviation of "AT attachment". The disk drive is
conformed to the ATA-3 interface. At high speed data transfer (PIO
mode 3, mode 4, or DMA mode 2 U-DMA mode 2), occurence of ringing or
crosstalk of the signal lines (AT bus) between the HA and the disk
drive may be a great cause of the obstruction of system reliability.
Thus, it is necessary that the capacitance of the signal lines
including the HA and cable does not exceed the ATA-3 standard, and
the cable length between the HA and the disk drive should be as short
The read/write circuit consists of two LSIs; read/write preamplifier
(PreAMP) and read channel (RDC).
The PreAMP consists of the write current switch circuit, that flows
the write current to the head coil, and the voltage amplifier
circuit, that amplitudes the read output from the head.
The RDC is the read demodulation circuit using the extended partial
response class 4 (EPR4), and contains the Viterbi detector,
programmable filter, adaptable transversal filter, times base
generator, and data separator circuits. The RDC also contains the
16/17 group coded recording (GCR) encoder and decoder and servo
The position and speed of the voice coil motor are controlled by 2
closed-loop servo using the servo information recorded on the data
surface. The servo information is an analog signal converted to
digital for processeing by a MPU and then reconverted to an analog
signal for control of the voice coil motor. The MPU precisely sets
each head on the track according on the servo information on the
Spindle motor driver circuit
The circuit measures the interval of a PHASE signal generated by
counter-electromotive voltage of a motor at the MPU and controls the
motor speed comparing target speed.
Major functions are listed below.
- Data buffer (512 KB) management
- ATA interface control and data transfer control
- Sector format control
- Defect management
- ECC control
- Error recovery and self-diagnosis
The disk drive occasionally performs self-calibration in order to
sense and calibrate mechanical external forces on the actuator, and
VCM tarque. This enables precise seek and read/write operations.
Self-calibration contents ------------------------- (1) Sensing and compensating for external forces The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned. To execute stable fast seek operations, external forces are occasionally sensed. The firmware of the drive measures and stores the force (value of the actuator motor drive current) that balances the torque for stopping head stably. This includes the current offset in the power amplifier circuit and DAC system.
The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control. To compensate torque varing by the cylinder, the disk is divided into 8 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration. The measured values are stored in the SA cylinder.
In the self-calibration, the compensating value is updated using the value in the SA cylinder.
(2) Compensating open loop gain Torque constant value of the VCM has a dispersion for each drive, and varies depending on the cylinder that the head is positioned.
To realize the high speed seek operation, the value that compensates torque constant value change and loop gain change of the whole servo system due to temperature change is measured and stored.
For sensing, the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder. The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio.
For compensating, the direction current value to the power amplifier is multiplied by the compensation value. By this compensation, loop gain becomes constant value and the stable servo control is realized. To compensate torque constant value change depending on cylinder, whole cylinders from most inner to most outer cylinder are divided into 8 partitions at calibration in the factory, and the compensation data is measured for representive cylinder of each partition. This measured value is stored in the SA area. The compensation value at self-calibration is calculated using the value in the SA area.
Execution timing of self-calibration
Self-calibration is executed when:
- The power is turned on.
- The disk drive receives the RECALIBRATE command from the host.
- The self-calibration execution timechart of the disk drive specifies self-calibration.
The disk drive performs self-calibration according to the timechart
based on the time elapsed from power-on. After power-on, self-
calibration is performed about every five or ten or fifteen minutes
for the first 60 minutes or six RECALIBRATE command executions, and
about every 30 minutes after that.
Spindle motor control
Hall-less three-phase twelve-pole motor is used for the spindle
motor, and the 3-phase full/half-wave analog current control circuit
is used as the spindle motor driver (called SVC hereafter). The
firmware operates on the MPU manufactured by Fujitsu. The spindle
motor is controlled by sending several signals from the MPU to the
SVC. There are three modes for the spindle control; start mode,
acceleration mode, and stable rotation mode.
(1) Start mode When power is supplied, the spindle motor is started in the following sequence: a) After the power is turned on, the MPU sends a signal to the SVC to charge the charge pump capacitor of the SVC. The charged amount defines the current that flows in the spindle motor.
b) When the charge pump capacitor is charged enough, the MPU sets the SVC to the motor start mode. Then, a current (approx. 0.7A) flows into the spindle motor.
c) The SVC generates a phase switching signal by itself, and changes the phase of the current flowed in the motor in the order of (V-phase to U-phase), (W-phase to U-phase), (W-phase to V-phase), (U-phase to V-phase), (U-phase to W-phase), and (V-phase to W-phase) (after that, repeating this order).
d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection.
e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode.
(2) Acceleration mode In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a phase switching by itself based on the counter electromotive force. Then, rotation of the spindle motor accelerates. The MPU calcurates a rotational speed of the spindle motor based on the PHASE signal from the SVC, and accelerates till the rotational speed reaches 4,000 rpm. When the rotational speed reaches 4,000 rpm, the SVC enters the stable rotation mode.
(3) Stable rotation mode The MPU calcurates a time for one revolution of the spindle motor based on the PHASE signal from the SVC. The MPU takes a difference between the current time and a time for one revolution at 4,000 rpm that the MPU already recognized. Then, the MPU keeps the rotational speed to 4,000 rpm by charging or discharging the charge pump for the different time. For example, when the actual rotational speed is 3,800 rpm, the time for one revolution is 15.789 ms. And, the time for one revolution at 4,000 rpm is 15ms. Therefore, the MPU discharges the charge pump for 0.789 ms ??k (k: constant value). This makes the flowed current into the motor lower and the rotational speed down. When the actual rotational speed is later than 4,000 rpm, the MPU charges the pump the other way. This control (charging/discharging) is performed every 1 revolution.
The device can operate for command execution in either address-
specified mode; cylinder-head-sector (CHS) or Logical block address
(LBA) mode. The IDENTIFY DEVICE information indicates whether the
device supports the LBA mode. When the host system specifies the LBA
mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0
bits of the Device/Head register indicates the head No. under the LBA
mode, and all bits of the Cylinder High, Cylinder Low, and Sector
Number registers are LBA bits.
The sector No. under the LBA mode proceeds in the ascending order
with the start point of LBA0 (defined as follows).
LBA0 = [Cylinder 0, Head 0, Sector 1]
Even if the host system changes the assignment of the CHS mode by the
INITIALIZE DEVICE PARAMETER command, the sector LBA address is not
EXECUTE DEVICE DIAGNOSTIC (X'90')
This command performs an internal diagnostic test (self-diagnosis) of
the device. This command usually sets the DRV bit of the Drive/Head
register is to 0 (however, the DV bit is not checked). If two devices
are present, both devices execute self-diagnosis.
If device 1 is present:
- Both devices shall execute self-diagnosis.
- The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG-signal.
- If the device 1 does not assert the PDIAG- signal but indicates an error, the device 0 shall append X'80' to its own diagnostic status.
- The device 0 clears the BSY bit of the Status register and generates an interrupt. (The device 1 does not generate an interrupt.)
- A diagnostic status of the device 0 is read by the host system.
When a diagnostic failure of the device 1 is detected, the host
system can read a status of the device 1 by setting the DV bit
(selecting the device 1).
When device 1 is not present:
- The device 0 posts only the results of its own self-diagnosis.
- The device 0 clears the BSY bit of the Status register, and generates an interrupt.
If the device 1 fails the self-diagnosis, the device 0 "ORs" X'80'
with its own status and sets that code to the Error register.
When the IDD receives any command which involves access to the disk
medium, the IDD always implements the address translation from the
logical address (a host-specified address) to the physical address
(logical to physical address translation).
Logical address assignment in the LBA mode starts from physical
cylinder 0, physical head 0, and physical sector 1. If the last
sector in a zone of a physical head is used, the track is switched
and the next LBA is assigned to the initial sector in the same zone
of the subsequent physical head. After the last physical sector of
the last physical head is used in the zone, the subsequent zone is
used and LBA is assigned from physical head 0 in the same way.
Standby mode - Sleep mode
The drive moves from the Active mode to the idle mode by itself.
Regardless of whether the power down is enabled, the device enters
the idle mode. The device also enters the idle mode in the same way
after power-on sequence is completed.
And, the automatic power-down is executed if no command is coming for
30 min. (default)
In this mode, all the electric circuit in the device are active or
the device is under seek, read or write operation.
A device enters the active mode under the following conditions:
- A command other than power commands is issued.
- A reset command is received.
In this mode, circuits on the device is set to power save mode.
The device enters the Idle mode under the following conditions:
- After completion of power-on sequence.
- After completion of the command execution other than SLEEP and STANDBY commands.
- After completion of the reset sequence
In this mode, the VCM circuit is turned off and the spindle motor is
The device can receive commands through the interface. However if a command with disk access is issued, response time to the command under the standby mode takes longer than the active or Idle mode because the access to the disk medium cannot be made immediately. The drive enters the standby mode under the following conditions: - A STANDBY or STANDBY IMMEDIATE command is issued in the active or idle mode.
- When automatic power down sequence is enabled, the timer has elapsed.
- A reset is issued in the sleep mode.