2.27 Cache terminology, what does it mean?
Description
This item is from the PC Hardware FAQ, by Willie Lim and Ralph Valentino with numerous contributions by others. (v1.25).
2.27 Cache terminology, what does it mean?
[From: cls@truffula.sj.ca.us (Cameron L. Spitzer)]
Why cache improves performance
Today's microprocessors ("uPs") need a faster memory than can be made with economical DRAMs. So we provide a fast SRAM buffer between the DRAM and the uP. The most popular way to set it up is by constructing a "direct mapped cache," which is the only setup I'll describe here.
Generic motherboard cache architecture
The direct mapped cache has three big features:
1. a "data store" made with fast SRAMs,
2 a "tag store" made with even faster SRAMs, and
3. a comparator.
The data store is the chunk of RAM you see in the motherboard price lists. It holds "blocks" or "lines" of data recently used by the CPU. Lines are almost always 16 bytes. The address feeding the cache is simply the least significant part of the address feeding main memory. Each memory location can be cached in only one location in the data store.
There are two "policies" for managing the data store. Under the "write-back" (or "copy-back") policy, the master copy of the data is in cache, and main memory locations may be "stale" at times. Under "write-through", writes go immediately to main memory as well as to cache and memory is never "stale."
The tag store mantains one "word" of information about each line of data in the data store.
In a "write-back" or "copy-back" cache, the tag word contains two items:
1. the part of the main memory address that was *not* fed to the data store, and
2. a "dirty" bit.
A write-through cache doesn't need a dirty bit. The tag store is addressed with the most significant address bits that are being fed to the data store. The tag is only concerned with the address bits that are used to select a line. With a 16 byte line, address bits 0 through 3 are irrelevant to the tag.
An example: The motherboard has 32 MB main memory and 256 KB cache. To specify a byte in main memory, 25 bits of address are required: A0 through A24. To specify a byte in data store, 18 bits (A0 through A17) are required. Lines in cache are 16 bytes on 16 byte boundaries, so only A4 through A17 are required to specify a line. The tag word for this system would represent A18 through A24 (plus dirty bit). The tag store in this system would be addressed by A4 through A17, therefore the tag store would require 16 K tag words seven bits wide. The dirty bit is written at different times than the rest of the tag, so it might be housed separately, and this tag store might be built in three 16K x4 SRAMs.
What happens when it runs
Each motherboard memory cycle begins when the uP puts out a memory address. The data store begins fetching, and simultaneously the tag begins fetching. When the tag word is ready, the Comparator compares the tag word to the current address.
If they match, a cache hit is declared and the uP reads or writes the data store location. If the hit is a write, the copy-back cache marks the line "dirty" by setting its dirty-bit in the line's tag word. The write-through motherboard simultaneously stores the write data in data store and begins a DRAM write cycle. The uP moves on.
If the tag word doesn't match, what a bummer, it's a cache miss. If the line in cache is dirty, double bummer, the line must be copied back to main memory before anything else can happen. All 16 bytes are copied back, even if the hit was a one-byte write. This data transfer is called a "dirty write flush."
On a read-miss, the motherboard has to copy a line from main memory to cache (and update the tag, the whole operation is called a "cache fill"), and the uP can stop waiting as soon as the bytes it wants go by. On a write-miss, the caches I've worked with ignore the event (that's an oversimplification) and the main memory performs a write cycle. I've heard of systems that fill on a write-miss, that is they replace the cache line whenever it misses, read or write, dirty or not. I've never seen such a system.
Terms
The 486, the 68020, and their descendants have caches on chip. We call the on-chip cache "primary" and the cache on the motherboard "secondary." The 386 has no cache, therefore the cache on a 386 motherboard is "primary." I like to call the DRAM array "core" for brevity. Motherboard = "mb." Megabyte = "MB."
Problems
I added "core" and I had to disable my secondary cache to get the board running. Or, I added core and performance took a dive. Disabling secondary cache improved it, but still real slow. What happened?
Whenever you are adding memory and you cross a power-of-2 address boundary, another address bit becomes interesting to the tag. That is, the tag does not care when you add your 8th MB (MB) but it cares a lot about the new address bit 24 when you add your 9th MB, or your 17th (bit 25). Evidently, at the low-price end of the mb market there are boards with not enough tag RAM sockets to support all the core they can hold. Most of these EL CHEAPO mbs don't even try to use cache in the region beyond the tag's coverage. Some of them don't have the logic to stay out or the BIOS doesn't know to enable it. These boards just don't run right.
Do not buy a mb if you are not sure it can cache all of core. The worst case is with core fully stuffed with whatever the board claims to hold, and the smallest cache configuration. Some motherboards ask you to add cache when you add core, so that they don't have to provide for that worst case tag width. These motherboards may ask you to move some jumpers in the tag area. The jumpers control which address bits the tag looks at. Do not buy a motherboard if you don't know how to set all the jumpers.
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