OCEAN INFORMATION SYSTEMS, INC.
HIPPO DCA2 486
Processor | 80486SX/SL80486SX/80487SX/CX486DX/80486DX/SL80486DX/ CX486DX2/AM486DX2/80486DX2/SL80486DX2/80486DX4/P24T |
Processor Speed | 25/33/50(internal)/66(internal)/75(internal)/100(internal)MHz |
Chip Set | Unidentified |
Video Chip Set | None |
Maximum Onboard Memory | 96MB |
Maximum Video Memory | None |
Cache | None |
BIOS | AMI/MR |
Dimensions | 279mm x 215mm |
I/O Options | 32-bit VESA local bus slots (3) |
NPU Options | None |

CONNECTIONS | |||
Purpose | Location | Purpose | Location |
Chassis fan power | JP2 | Speaker | P4 |
Reset switch | P1 | Power LED & keylock | P5 |
Turbo switch | P2 | External battery | P8 |
Turbo LED | P3 | 32-bit VESA local bus slots | SL1 - SL3 |
Note: JP2 may not be present. | |||
USER CONFIGURABLE SETTINGS | |||
Function | Label | Position | |
» | Fan voltage select 12v | JP1 | Pins 2 & 3 closed |
Fan voltage select 5v | JP1 | Pins 1 & 2 closed | |
» | Reserved for future use (CPU signal reset source) | JP5 | Pins 1 & 2 closed |
» | Reserved for future use (SL CPU select) | JP13 | Pins 2 & 3 closed |
» | Reserved for future use (CPU multiplier 2.5x) | JP16 | Open |
» | Reserved for future use (CPU multiplier 2x) | JP17 | Open |
» | Reserved for future use (EPMI) | JP18 | Open |
» | CMOS memory normal operation | JP19 | Pins 2 & 3 closed |
CMOS memory clear | JP19 | Pins 1 & 2 closed | |
» | Power good signal detect from power supply | JP20 | Pins 1 & 2 closed |
Power good signal detect from board | JP20 | Pins 2 & 3 closed | |
» | Monitor type select color | JP21 | Pins 1 & 2 closed |
Monitor type select monochrome | JP21 | Pins 2 & 3 closed | |
» | Reserved for future use (Cyrix voltage select 3.3v) | JP22 | Open |
» | Reserved for future use (Cyrix voltage select 3.6v) | JP23 | Open |
» | Reserved for future use (Cyrix voltage select 3.8v) | JP24 | Open |
» | Reserved for future use (Cyrix voltage select 4v) | JP25 | Open |
» | Reserved for future use (Intel/AMD CLKMUL) | JP26 | Pins 1 & 2 closed |
» | Reserved for future use (Intel/AMD voltage 3.45v/5v) | JP27 | Closed |
» | Reserved for future use (force voltage to 5v) | JP28 | Open |
DRAM CONFIGURATION | ||||
Size | Bank 0 | Bank 1 | Bank 2 | Bank 3 |
4MB | (1) 1M x 36 | None | None | None |
6MB | (1) 1M x 36 | None | (1) 512K x 36 | None |
8MB | (1) 1M x 36 | None | (1) 512K x 36 | (1) 512K x 36 |
8MB | (1) 1M x 36 | (1) 1M x 36 | None | None |
8MB | (1) 2M x 36 | None | None | None |
12MB | (1) 1M x 36 | None | (1) 2M x 36 | None |
12MB | (1) 1M x 36 | (1) 1M x 36 | (1) 1M x 36 | None |
12MB | (1) 1M x 36 | (1) 2M x 36 | None | None |
12MB | (1) 2M x 36 | None | (1) 1M x 36 | None |
16MB | (1) 1M x 36 | (1) 1M x 36 | (1) 1M x 36 | (1) 1M x 36 |
16MB | (1) 1M x 36 | (1) 1M x 36 | (1) 2M x 36 | None |
DRAM CONFIGURATION (CON’T) | ||||
Size | Bank 0 | Bank 1 | Bank 2 | Bank 3 |
16MB | (1) 2M x 36 | None | (1) 1M x 36 | (1) 1M x 36 |
16MB | (1) 2M x 36 | None | (1) 2M x 36 | None |
16MB | (1) 2M x 36 | (1) 2M x 36 | None | None |
16MB | (1) 4M x 36 | None | None | None |
20MB | (1) 1M x 36 | None | (1) 2M x 36 | (1) 2M x 36 |
20MB | (1) 1M x 36 | (1) 2M x 36 | (1) 2M x 36 | None |
24MB | (1) 1M x 36 | (1) 1M x 36 | (1) 2M x 36 | (1) 2M x 36 |
24MB | (1) 1M x 36 | (1) 1M x 36 | (1) 4M x 36 | None |
24MB | (1) 2M x 36 | None | (1) 2M x 36 | (1) 2M x 36 |
24MB | (1) 2M x 36 | None | (1) 4M x 36 | None |
24MB | (1) 2M x 36 | (1) 2M x 36 | (1) 2M x 36 | None |
24MB | (1) 4M x 36 | None | (1) 2M x 36 | None |
28MB | (1) 1M x 36 | (1) 1M x 36 | (1) 4M x 36 | (1) 1M x 36 |
28MB | (1) 2M x 36 | None | (1) 4M x 36 | (1) 1M x 36 |
32MB | (1) 2M x 36 | (1) 2M x 36 | (1) 2M x 36 | (1) 2M x 36 |
32MB | (1) 2M x 36 | (1) 2M x 36 | (1) 4M x 36 | None |
32MB | (1) 4M x 36 | None | (1) 2M x 36 | (1) 2M x 36 |
32MB | (1) 4M x 36 | None | (1) 4M x 36 | None |
32MB | (1) 4M x 36 | (1) 4M x 36 | None | None |
40MB | (1) 1M x 36 | (1) 1M x 36 | (1) 4M x 36 | (1) 4M x 36 |
40MB | (1) 1M x 36 | (1) 1M x 36 | (1) 8M x 36 | None |
40MB | (1) 2M x 36 | None | (1) 4M x 36 | (1) 4M x 36 |
40MB | (1) 2M x 36 | None | (1) 8M x 36 | None |
48MB | (1) 2M x 36 | (1) 2M x 36 | (1) 4M x 36 | (1) 4M x 36 |
48MB | (1) 2M x 36 | (1) 2M x 36 | (1) 8M x 36 | None |
48MB | (1) 4M x 36 | None | (1) 4M x 36 | (1) 4M x 36 |
48MB | (1) 4M x 36 | None | (1) 8M x 36 | None |
48MB | (1) 4M x 36 | (1) 4M x 36 | (1) 4M x 36 | None |
64MB | (1) 4M x 36 | (1) 4M x 36 | (1) 4M x 36 | (1) 4M x 36 |
64MB | (1) 4M x 36 | (1) 4M x 36 | (1) 8M x 36 | None |
72MB | (1) 1M x 36 | (1) 1M x 36 | (1) 8M x 36 | (1) 8M x 36 |
72MB | (1) 2M x 36 | None | (1) 8M x 36 | (1) 8M x 36 |
80MB | (1) 2M x 36 | (1) 2M x 36 | (1) 8M x 36 | (1) 8M x 36 |
80MB | (1) 4M x 36 | None | (1) 8M x 36 | (1) 8M x 36 |
96MB | (1) 4M x 36 | (1) 4M x 36 | (1) 8M x 36 | (1) 8M x 36 |
Note: Banks 0 & 1 only accept Dynamicache modules. | ||||
CPU SPEED SELECTION | ||
Speed | JP3 | JP4 |
25MHz | Pins 1 & 2 closed | Pins 1 & 2 closed |
33MHz | Pins 2 & 3 closed | Pins 2 & 3 closed |
50iMHz | Pins 1 & 2 closed | Pins 1 & 2 closed |
66iMHz | Pins 2 & 3 closed | Pins 2 & 3 closed |
75iMHz | Pins 1 & 2 closed | Pins 1 & 2 closed |
100iMHz | Pins 2 & 3 closed | Pins 2 & 3 closed |
CPU TYPE SELECTION | ||||||
Type | JP6 | JP7 | JP8 | JP10 | JP14 | JP15 |
80486SX | Open | Open | Open | 2 & 3 | 2 & 3 | 2 & 3 |
SL80486SX | Open | Open | Open | 2 & 3 | 2 & 3 | 2 & 3 |
80487SX | Open | Open | 2 & 3 | 1 & 2, 3 & 4 | 2 & 3 | 2 & 3 |
CX486DX | Open | 2 & 3 | 1 & 2 | 1 & 2, 3 & 4 | 2 & 3 | 2 & 3 |
80486DX | Open | Open | 1 & 2 | 1 & 2, 3 & 4 | 2 & 3 | 2 & 3 |
SL80486DX | Open | Open | 1 & 2 | 1 & 2, 3 & 4 | 2 & 3 | 2 & 3 |
CX486DX2 | Open | 1 & 2 | 1 & 2 | 1 & 2, 3 & 4 | 2 & 3 | 2 & 3 |
AM486DX2 | Open | Open | 1 & 2 | 1 & 2, 3 & 4 | 2 & 3 | 2 & 3 |
80486DX2 | Open | Open | 1 & 2 | 1 & 2, 3 & 4 | 2 & 3 | 2 & 3 |
SL80486DX2 | Open | Open | 1 & 2 | 1 & 2, 3 & 4 | 2 & 3 | 2 & 3 |
80486DX4 | Open | Open | 1 & 2 | 1 & 2, 3 & 4 | 2 & 3 | 2 & 3 |
P24T | Open | Open | 1 & 2 | 1 & 2, 3 & 4 | 2 & 3 | 2 & 3 |
VL BUS WAIT STATE SELECTION | ||
Setting | JP12 | |
0 | Pins 2 & 3 closed | |
| » | 1 | Pins 1 & 2 closed |
VL BUS SPEED SELECTION | ||
Setting | JP11 | |
| » | <= 33MHz | Pins 2 & 3 closed |
>33 MHz | Pins 1 & 2 closed | |
VL BUS SELECTION | |||
Setting | JP9 | JW1 | |
| » | Synchronous | Open | Pins 2 & 3 closed |
Nonsynchronous | Pins 2 & 3 closed | Pins 1 & 2 closed | |
MISCELLANEOUS TECHNICAL NOTE |
The location of pin 1 on all jumpers is unidentified. |