DTK COMPUTER, INC.
PKM-5031Y
Processor | 80486SX/80487SX/80486DX/ODP486SX/80486DX2 |
Processor Speed | 16/20/25/33/50(internal)/50/66(internal)MHz |
Chip Set | Symphony |
Max. Onboard DRAM | 32MB |
Cache | 64/256KB |
BIOS | AMI/DTK |
Dimensions | 330mm x 218mm |
I/O Options | None |
NPU Options | None |
CONNECTIONS | |||
Purpose | Location | Purpose | Location |
Reset switch | J1 | Turbo LED | J4 |
Turbo switch | J2 | Power LED & keylock | J5 |
Speaker | J3 |
USER CONFIGURABLE SETTINGS | |||
Function | Jumper | Position | |
» | CPU speed select forced high | J2 | Open |
CPU speed select switchable at keyboard | J2 | pins 2 & 3 closed | |
» | Cache write select 0 wait states | J9 | Closed |
Cache write select 1 wait state | J9 | Open | |
» | Monitor type select monochrome | J13 | pins 1 & 2 closed |
Monitor type select color | J13 | pins 2 & 3 closed |
DRAM CONFIGURATION | ||
Size | Bank 0 | Bank 1 |
1MB | (4) 256K x 9 | NONE |
2MB | (4) 256K x 9 | (4) 256K x 9 |
4MB | (4) 1M x 9 | NONE |
5MB | (4) 256K x 9 | (4) 1M x 9 |
8MB | (4) 1M x 9 | (4) 1M x 9 |
16MB | (4) 4M x 9 | NONE |
17MB | (4) 256K x 9 | (4) 4M x 9 |
20MB | (4) 1M x 9 | (4) 4M x 9 |
32MB | (4) 4M x 9 | (4) 4M x 9 |
CACHE CONFIGURATION | ||
Size | Bank 0 | TAG |
64KB | (8) 8K x 8 | (1) 8K x 8 |
256KB | (8) 32K x 8 | (1) 32K x 8 |
CACHE JUMPER CONFIGURATION | |||
Size | J6 | J7 | J8 |
64KB | pins 1 & 2 closed | pins 1 & 2 closed | pins 1 & 2 closed |
256KB | pins 2 & 3 closed | pins 2 & 3 closed | pins 2 & 3 closed |
CPU TYPE CONFIGURATION | |||
Type | J10 | J11 | J12 |
80486SX | Open | pins 2 & 3 closed | Open |
80486DX | Closed | pins 1 & 2 closed | Closed |
80486DX2 | Closed | Closed |
CPU SPEED CONFIGURATION | |||||
Speed | J14 | J15 | J16 | J17 | J18 |
16MHz | Closed | Open | Open | 1 & 2 | Open |
20MHz | Closed | Open | Open | 1 & 2 | Open |
25MHz | Closed | Open | Open | 1 & 2 | Open |
33MHz | Closed | Open | Open | 1 & 2 | Open |
50iMHz | Closed | Open | Open | 1 & 2 | Open |
50Mhz (15ns cache) | Open | Closed | Open | 2 & 3 | Closed |
50Mhz (20ns cache) | Closed | Closed | Closed | 2 & 3 | Closed |
66iMHz | Closed | Open | Open | 1 & 2 | Open |
Note: Pins designated should be in the closed position. |