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A L - 2 5 4 0     C A V I A R   L I T E    WESTERN DIGITAL
NO MORE PRODUCED                                      Native|  Translation
Form                 2.5"/SUPERSLIMLINE    Cylinders        | 1048|     |
Capacity form/unform   540/      MB        Heads           4|   16|     |
Seek time   / track  16.0/ 4.0 ms          Sector/track     |   63|     |
Controller           IDE / ATA2 FAST/ENHA  Precompensation
Cache/Buffer           128 KB ADAPTIVE     Landing Zone
Data transfer rate    5.000 MB/S int       Bytes/Sector      512
                     16.600 MB/S ext PIO4
Recording method                                    operating  | non-operating
Supply voltage     5 V          Temperature *C         5 55    |    -40 60
Power: sleep              W     Humidity     %         8 85    |      5 95
       standby        0.1 W     Altitude    km                 |
       idle           1.4 W     Shock        g        30       |    300
       seek               W     Rotation   RPM      4500
       read/write     2.5 W     Acoustic   dBA
       spin-up        3.5 W     ECC        Bit   REED SOLOMON
                                MTBF         h     300000
                                Warranty Month        24
Lift/Lock/Park     YES          Certificates     ISO9001                      


WESTERN AL-2540 TECHNICAL REFERENCE MANUAL 79-860014-000 31/08/1995

  |                                                         |XX
  |                                                         |XX
  |                                                         |XX
  |                                                         |XX J2
  |                                                         |XX Inter-
  |                                                         |XX face
  |                                                         |XX
  |                                                         |.X
  |                                                         |XX
  |                                                         |XX
  |                                                         |XX
  |                                                         |XX
  |                                                         |XX
  |                                                         |1X
  |                                                         |+-+J8
  |                                                         |1-2

                                                    S M
                                                    L S
                                                    V T
     |o o o o o o o o o o o o o o o o o o o o o o . o o |J8
     |o o o o o o o o o o o o . o o o o o o o o o . o o |

J2 pin 20 keyed


WESTERN AL2540 TECHNICAL REFERENCE MANUAL 79-890014-000 31/08/1995

Jumper setting

J8 Master/Slave/Cable Select Configuration

    +3-1+ Single Drive              +3-1+ Master Drive
    |o o| Configuration             |o X| Configuration
    |o o|                           |o X|
    +4-2+                           +4-2+

    +3-1+ Slave Drive               +3-1+ Cable Select
    |X o| Configuration             |X X| Configuration
    |X o|                           |X X|
    +4-2+                           +4-2+

The Caviar can be assigned as either a single, master, or slave, or
CSEL drive.

Dual Installations
Dual installations require a master/slave drive configuration, where
one drive is designated as the primary (master) drive and the other
is designated as the secondary (slave) drive. The Caviar Lite drive
is compatible in dual installations with other intelligent drives
that support a master/slave configuration.

Another dual installation uses CSEL. When both master and slave
jumper are installed, then the CSEL line dictates the master or slave
drive identity.

Single/Master Drive Mode
The AL2540 drive autodetects which mode to enter by checking the
Drive Active/Slave Present (DASP) signal to determine if a slave is
present. If a slave is not detected, the drive enters single mode
operation. If a slave is detected, the AL2540 drive enters master
mode operation.

Cable Select (CSEL)
Caviar Lite also supports the CSEL signal on the drive cable as a
drive address selection. Place a jumper shunt on pins 3-4 and 1-2 to
enable this option. When enabled, the drive address is 0 (Master) if
CSEL is low, or 1 (Slave) if CSEL is high.

Do not install the CSEL jumper shunts when installing the Caviar Lite
drive on systems that do not support the CSEL feature.

Dual Drive Option
The AL2540 drive supports ATA-2 dual drive operations with
configuration options for master or slave drive designation. The
AL2540 drive is 100% ATA-2 compatible regarding the timing of the
PDIAG and DASP signals. A jumper must be placed in the drive's
option area for slave configurations. If both master and slave are
selected, the drive address selection is determined by the CSEL
signal on the drive cable. The drive are connected to the host by


WESTERN AL2540 TECHNICAL REFERENCE MANUAL 79-860014-000 31/08/1995

Notes of Installation

The AL2540 drive can be mounted in the X, Y, or Z axis depending on
the physical design of your system. It is recommended that the drive
be mounted with all four screws grounded to the chassis.

Screw Size Limitations
The AL2540 drive is mounted to the chassis using four M3.0X5-6H
screws. Recommended screw torque is 5 inch-pounds. Maximum screw
torque is 10 inch-pounds.

The screw must engage the threads in the mounting bosses no more than
0.118 inches (3mm) in side mounts and no more than 0.098 inches
in bottom mounts.

It is strongly recommended that the drive be mounted with all four
screws in the side grounded to the chassis.

Determining Your Configuration
The drive is cabled directly to a 44-pin connector on the mother-
board using a 44-pin host interface cable.

In dual installations, you must use a 44-pin host interface cable
with three connectors and daisy-chain the two drives to the
motherboard or adapter card.

Cabling and Installation Steps
Make sure your interface cable is no longer than 18 inches to
minimize the noise which is induced on the data and control buses.
Also, if you are connecting two drives together, you need a daisy-
chain-cable that has three 44-pin connectors.

Caution: You may damage the Caviar Lite drive if the interface
cable is not connected properly. To prevent incorrect connection,
use a cable that has keyed connectors at both the drive and host
ends. Pin 20 has been removed from J2 connector. The female connector
on the interface cable shoul have a plug position 20 to prevent
incorrect connection. Make sure that pin 1 on the cable is connected
to pin 1 on the connectors.

Universal Translation
The AL2540 drive implements linear address translation. The
translation mode and translated drive configuration are selected by
using the Set Drive Parameters command to issue head and sector/track
counts to the translator. AL2540 drive supports universal
translation. Therefore, any valid combination of cylinder, head and
SPT can be assigned to the drive, as long as the total number of
sectors is not greater than the physical limits. The product of the
cylinder, head and sectors/track counts must be equal to or less than
the maximum number of sectors available to the user. The maximum
number of sectors is 1,056,384.

Each sector consists of 512 bytes.

The minimum values for any translation parameter is one.
The maximum value for any translation parameter is as follows:

Sectors/Track - 255
Heads - 16
Cylinders/Drive - 2048

The values in the Sector Count Register and the SDH Register de-
termine the sectors per track (SPT) and heads. Regardless of the
Values of the SPT and the heads, the AL2540 drive is always in the
translation mode.


WESTERN AL2540 TECHNICAL REFERENCE MANUAL 79-860014-000 31/08/1995

General Description
The Western Digital AL2540 Enhanced IDE provides 540 MB of formatted
storage in a low profile 12.7-mm high 2.5-inch form factor. The
light weight AL2540 is designed for use in AT-compatible notebooks
and ultralights. It is a premier storage solution achieving
unsurpassed reliability with optimum performance for notebooks.

Advanced Defect Management
The Caviar Lite is preformatted (low-level) at the factory and comes
with a full complement of defect management functions. Extensively
tested during the manufacturing process, media defects found during
intelligent burn in are mapped out with Western Digital's high
performance defect management technique. No modifications are
required before installation.

Embedded Servo Control
The Caviar Lite features an embedded servo concept that samples and
feeds back position information to the head position servo system.
Servo bursts are located along a radial path from the disk center,
ensuring that head positioning data occurs at constant intervals.
This high sampling rate supports the high frequency servo bandwidth
required for fast access times as well as highly accurate head
positioning. The embedded servo concept provides the means of
generating accurate feedback information without requiring a full
data surface as does dedicated servo control.

Seek Time
Average Seek Read 13 Milliseconds

Track-to-Track Seek 4 Milliseconds

Maximum Seek 23 Milliseconds

Index Pulse Period 13.3 Milliseconds

Average Latency 6.7 Milliseconds

Defect Management
Every Caviar Lite undergoes factory-level intelligent burn in, which
thoroughly tests for and maps out defective sectors on the media
before the drive leaves the manufacturing facility. Following the
factory tests, a primary defect list is created. The list contains
the sector cylinder and head numbers for all defects.

Defects managed at the factory are sector slipped. Grown defects that
can occur in the field are handled by realocation to spare sectors on
the inner cylinders of the drive.

Automatic Defect Retirement
If the AL2540 detects a defective sector while writing, if automatic-
ally relocates the sector without end user intervention.

Format Characteristics
Before the AL2540 drive is shipped from the factory, low-level
preformatting is performed and known defects are mapped out.

In order to be compatible with existing industry standard defect
management utility programs, the Caviar Lite supports the logical
format command. When the host issues the Format Track command, the
data fields of the specified track are filled with a pattern of all
zeros. The Format Track command can also be used to mark/unmark bad
sectors, or assign/unassign sector(s) to/from an alternate sector.

The AL2540 features CacheFlow3, Western Digital's third generation
advanced caching algorithm. CacheFlow3 increases performance by
adapting read and write methodology on-the-fly and works in
conjunction with the advanced disk caching capabilities of today's
major operating systems. New random write caching improves random
write performance up to 30 percent.

WESTERN DIGITAL Defect Management Utility
All Caviar IDE drives are defect-free and low level formatted at the
factory. After prolonged use, any drive, including Caviar, may
develop defects. If you continue receiving data errors in any given
file at the DOS level, you can use the defect management utility
WDAT_IDE to recover, relocate and rewrite the user data to the
nearest spare sector and maintain a secondary defect list.

Caution: As with all format utilities, some options in the WDAT_IDE
utility will overwrite user data.

ECC On-the-Fly
If an ECC error occurs, the AL2540 drive attempts to correct it
on-the-fly without retries. Data can be corrected in this manner
without performance penalty.

Password Security
The AL2540 drive implements a password protection scheme that uses
six commands to protect the drive from unauthorized use. The host
system can create, delete, freeze, lock, and unlock the drive. The
drive aborts all read and write operations once a password is set. To
unlock the drive, send it a password that matches the current one.

Theory of Operation
The host sends 512 bytes containing a two-byte identifier word and
a 32-byte password via the Set Password command. There are two
security levels: High and Maximum. The 2-byte identifier word is
used to specify the password type (master or user) and the security
leevel (high or maximum).

When powered-on, the drive determines if a password is currently
active. if so, it aborts all reads and writes until it receives a
Disable or Unlock command with the correct password. The Identify
Drive command returns the status of the drive security settings.

The system BIOS can determine if the drive password is set using the
Identify command. Using the password it can issue a Drive Unlock
command. When the drive is unlocked, the BIOS should issue a Freeze
Lock command to reject any other password commands until drive
power is cycled.

Password Types and Drive Security Levels
When you sert the password, you designate it as User or Master. You
also designate the security level as High or Maximum. These settings
determine which password can unlock the drive. Whenever drive power
is cycled, the drive is locked, and the appropriate password must
sent to unlock it. The following table shows the security/password
combinations and the password they require to unlock the drive.

 |Set Password Type |  Security Level | Unlocking Password|
 |User              |  High           | User or Master    |
 |User              |  Maximum        | User only         |
 |Master            |  High           | User or Master    |
 |Master            |  Maximum        | User only         |

Disable Password (F6h)
If you send a Disable Password command with the valid User password,
the User password is erased from the drive, and the drive is un-
locked allowing uncontrolled access.

The AL2540 implements Reed Solomon error correction techniques in
hardware to reduce the uncorrectable read error rate. This allows a
high degree of data integrity with no impact on the drive's
performance. Because on-the-fly corrected errors do not require the
drive's firmware to assist with error correction, they are invisible
to the host system.

To obtain the ECC check byte values, each byte within the sector is
interleaved into one of three groups, where the first byte is in
interleave 1, the second byte is in interleave 2, the third byte is
in interleave 3, the fourth byte is in interleave 1, and so on.

Interleaving and the ECC formulas enable the drive to detect where
the error occurs. A maximum of one byte can be corrected in each
interleave without firmware assistance.

Firmware Assisted ECC
With firmware assisted ECC, a maximum of 3 bytes can be corrected in
each interleave. In this case, a 65-bit error span is the maximum
that is always correctable with firmware assistance because the
entire error span will never occupy more than three bytes in each

Execute Diagnostics (90H)
The Execute Diagnostics command causes the Caviar to execute its
self-diagnostics and to report a result code in the Error Register
as follows:

     01 = No Error
     02 = Not Applicable
     03 = Buffer RAM Error
     04 = WD61C28 Register Error
     05 = Microcontroller Internal RAM Error or ROM Checksum Error
     8x = Slave Drive Failed.

Logical Block Addressing (LBA)
The AL2540 drive supports Logical Block Addressing mode. LBA allows
sectors on the drive to be addressed by using cylinder, head, and
sector numbers, or ny using a single 28-bit logical block address.
LBA mode is enabled by setting bit 6 in the SDH task file register.



Enhanced IDE Backgrounder

The Computer Market and the IDE Interface:
The computer marketplace is segmented into various classes of
machines divided by user expectations in terms of cost, performance,
compatibility and ease-of-use. The largest distinct segment today is
the personal computer market, characterized by single- user products
supporting a broad user base. The usage of these machines in business
and home environments has dictated an emphasis on cost and
compatibility. Historically, cost and compatibility in the personal
computer marketplace have been more important to mainstream users
than very high performance. The PC user has simply not been willing
to bear the added cost or potential lack of compatibility that
highest performance solutions imply.

Given this criteria, the mainstream volume personal computer market
has standardized on the IDE interface for its primary storage needs.
The success of the IDE interface in the PC market has resulted
primarily from a perfect match between IDE's offerings and the
requirements of the market it serves. Specifically, its low cost of
connection, compatibility, and ease-of-use, compared to alternative
interfaces such as the Small Computer System Interface (SCSI), have
been essential attributes in satisfying an expansive price-sensitive
user group. In addition, because of the broad user base it serves,
the personal computer market has traditionally required only hard
disk support to meet its mass storage requirements. IDE has therefore
evolved as a drive-only interface.

Increasing Need for Performance and Connectivity Flexibility:
As the personal computer market matures, it continues to display an
increased emphasis on enhanced performance and connectivity
capabilities, while maintaining its focus on cost, compatibility and
ease-of-use. The market criteria has therefore grown to include
higher performance attributes without sacrificing the needs of its
price sensitive customers. It is in the realm of higher performance
characteristics and connectivity that today's traditional IDE
interface faces challenges. Other existing interfaces, such as SCSI,
provide greater flexibility and performance options to meet these
requirements, while failing to provide IDE's benefits of
compatibility, cost and ease-of-use.

Western Digital's Enhanced IDE technology addresses the performance
and connectivity challenges facing the IDE interface. Enhanced IDE is
designed to extend the attributes of the IDE interface so that its
characteristics more effectively match the new requirements of the
evolving personal computer market, without forfeiting its traditional

Western Digital and the IDE Interface - Building upon Expertise:
Western Digital's Enhanced IDE technology evolves from the company's
storage expertise within the personal computer marketplace. In 1984,
Western Digital developed the WD1002 floppy and ST506 interface hard
disk controller that IBM utilized in their PC/AT systems. The success
of the PC/AT architecture led to the massive growth of the IBM PC/AT
compatible market. This dramatic growth was in part fueled by WD1002
compatible hard disk controllers and later by Western Digital's
standard-setting WD1003 series of AT controllers.

As the market expanded and became more price sensitive, Western
Digital defined the need for integration of the AT controller
electronics within the disk drive. By working with Compaq Computer
Corporation, Western Digital again drove the technology by proposing
the IDE (Integrated Drive Electronics) interface which was
implemented in the industry's first IDE drive in 1986. The disk
drives used in personal computers have standardized around IDE since
this introduction.

ATAPI Specification:
Now, Western Digital continues to lead the industry with its IDE
interface expertise via Enhanced IDE, an approach that expands upon
the existing attributes of the IDE interface and extends its usage
into more demanding environments. Enhanced IDE not only incorporates
high speed host transfer capabilities, support of high capacity disk
drives, and multiple device connectivity, but it also includes
non-disk peripheral support via the Western Digital authored ATAPI
(AT Attachment Packet Interface) specification. This
enhanced IDE-ATA specification enables connectivity of non-disk
peripherals such as CD-ROM and tape drives. The Western Digital
defined ATAPI specification, with participation and endorsement by
key market-making OEMS, CD-ROM suppliers and operating system
suppliers, is yet another example of Western Digital's commitment to
the evolution of the IDE interface.

Enhanced IDE:
Enhanced IDE removes many of the existing limitations and issues
associated with the current IDE interface. Removal of these
limitations enables IDE to grow with the industry's increased mass
storage requirements without sacrificing its key cost, compatibility
and ease-of- use attributes. The historical limitations of IDE
relative to other interfaces, such as SCSI, have not threatened IDE's
dominance of the PC marketplace to date. Upcoming personal computer
systems, architected around high performance processors, more complex
operating systems, and more demanding software applications, have
developed storage requirements beyond the realm of today's IDE
capabilities, challenging IDE's dominant role in the PC market.

Specifically, the IDE interface is less flexible and limited in key
areas of performance and connectivity relative to the SCSI interface:

     The IDE interface supports two disk drives. The SCSI interface
     supports multiple devices includingprinters, CD-ROM, tape drives
     as well as hard disk drives.

     The IDE interface is limited to 528MB hard disk capacity as a
     result of the Int 13h BIOS interface used to access IDE
     drives. The SCSI interface is not limited in capacity. The
     IDE interface typically offers 2-3MB/sec host transfer rates
     on standard ISA bus architected machines. The SCSI interface
     offers 10MB/sec FAST transfers and up to 20MB/sec FAST/WIDE
     host throughput.

Western Digital's Enhanced IDE technology offers solutions to the
existing constraints associated with the current IDE interface such
as capacity limitations, slower host transfers, and connectivity
issues associated with the IDE interface and thereby enables a cost
effective, compatible, and easy-to-use interface solution for the
next generation of personal computers.

Components of Enhanced IDE:
Enhanced IDE focuses on removing four primary limitations of the
existing IDE interface. These include:

      Removal of the 528MB capacity barrier
      Breaking the IDE transfer bottleneck
      Supporting multiple IDE devices
      Enabling non-disk peripheral connectivity, such as CD-ROM

Below, each of these limitations is discussed and resolved in detail.

Removal of Capacity Limitations
A barrier in implementing IDE disk drives greater than 528MB exists
in today's standard AT system BIOS. This barrier is based on
historical reasons dating from the development of the original AT
machine in 1984. Specifically, it is a limitation of the combined
Interrupt 13 software interface and the IDE interface. The goal is to
change the system BIOS such that this barrier no longer exists,
thereby enabling the usage of high capacity IDE disk drives. Western
Digitial's specification for removing the 528MB barrier is a simple
yet effective method for implementation by BIOS suppliers and system
manufactures who write their own BIOS.

The capacity limitation exists due to the number of bits allocated
for specifying the cylinder, head, and sector address information at
both the Int 13h interface level and at the IDE interface level.
Because Int 13h and IDE specify differing values, combining these two
interfaces produces an artificial 528MB barrier as shown below:

                                  BIOS          IDE
 Limitation Max Sectors/Track      63           225           63
 Number of Heads                  255            16           16
 Number of Cylinders             1024         65536         1024
 Maximum Capacity               8.4GB       136.9GB        528MB

Two solutions exist that resolve the existing 528MB barrier problem.
The first method is to have the BIOS translate the CHS address at the
13h interface to the CHS parameters being used at the drive
interface. The Enhanced IDE proposal to break the 528MB barrier is to
utilize the second method of modifying the Int 13h BIOS so that it
translates the cylinder, head, sector information passed to it via
Int 13 into a 28 bit Logical Block Address (LBA). The LBA solution is
believed to be the best method of breaking the 528MB barrier because
it provides a clean and efficient way for future operating system
drivers to access IDE drives.

The LBA translation is loaded into the drive's task file registers.
Bit 6 of the drive's SDH register is set to indicate to the drive's
firmware that it should interpret the information in its task file
registers as LBA rather than cylinder, head and sector information.
This scheme will allow for the full use of all of the bits allocated
for CHS information at the Int 13h interface, thereby supporting up
to 8.4GB.

Using a logical block addressing scheme is attractive primarily
because it is 100 percent compatible with BIOS Int 13 and allows for
reduced overhead, producing higher performance. The logical block
addressing scheme provides the compatibility essential for personal
computer usage as well as enables the implementation of higher
capacity disk drives required for high performance machines.

Western Digital's LBA scheme has been successfully demonstrated by
key system manufacturers writing their own BIOS and by those working
in conjunction with their BIOS suppliers. Systems shipping in
calendar Q4, 1993 will implement this scheme with the Western Digital
Caviar AC2540.

Bypassing the AT-IDE Host Transfer Bottleneck:
The ISA bus capabilities are designed to sustain host throughput data
rates of roughly 2-3MB/sec. Relative to SCSI host transfer rates of
5MB, 10MB, and 20MB/sec, the ISA bus is painfully slow for higher
performance applications. Because AT personal computers did not
necessarily demand the higher performance obtained by their
workstation or file server counterparts, 2-3MB/sec wasn't considered
a limiting factor. In addition, the ISA bus capabilities of 2-3MB/sec
did not present a throughput problem because data rates coming off
the media were roughly only 5Mbits/sec, and not a challenge to the
host throughput.

As disk drive areal density technologies progressed, media data rates
began to exceed the 2-3MB/sec ISA host throughput. Buffering either
on the system or the drive was necessary to maintain performance. The
industry's most recent drive offerings far exceed the ISA bus host
throughput by providing media data rates of up to 48Mbit/sec. Due to
these factors, increased buffering is not a cost effective
alternative to faster host throughput.

Fast PIO Transfers:
Other peripherals within the computer, such as video, resolved their
throughput problems via local bus architectures providing a potential
path for improved performance. IDE local bus solutions, leveraged
from the success of video local bus, began appearing in 1992, as a
way to enhance data throughput. These solutions mapped the IDE data
port to the local bus, bypassing the ISA bus and enabling the
maximization of throughput from the media to the drive buffer, on to
the host. These solutions were still not competitive with Fast SCSI
(10MB/sec) due to the "blind" transfer nature of the PIO transfers.
"Blind PIO" transfers indicate host control of data throughput with
the host requesting data (master) and the drive responding (slave).
With blind PIO transfers, the host is unaware or "blind" when
buffered drive bandwidth is 100% available for host transfers.
Because there are cases when only a percentage of bandwidth is
available, blind PIO host requests for data from the drive are based
on the worst case bandwidth availability. This means that even when
the ISA bottleneck is bypassed by connection directly to the local
bus, inability to utilize 100% drive bandwidth prevents full
optimization of host throughput.

Enhanced IDE incorporates an operation called "Flow Control Using
IORDY" (I/O Channel Ready) which allows the drive to "throttle" the
host when necessary and enable burst transfers to take advantage of
100% of the bandwidth. Flow Control thereby gives control of the data
transfer to the drive and eliminates the inefficiencies of blind PIO
by setting the host to maximum drive bandwidth support. This means
that when 100% drive bandwidth is available, the drive will take
control and transfer data to the host.

This operation, based on approved Mode 3 PIO timings of 180ns cycle
times from the Small Form Factor Committee, supports transfer rates
up to 11MB/sec competitive with FAST SCSI solutions. Flow Control is
enabled on the drive by the host issuing a Set Features command, so
that both the host and drive side support this operation. Western
Digital's 540MB drives (shipping beginning September, 1993) support
flow control using IORDY and will be implemented into machines that
take advantage of this feature via low cost ASICS whose functionality
will later be incorporated into core logic chipset solutions.

DMA Transfers
Although PIO is the standard transfer method supported by the
industry and presents no incompatibility issues (see footnote),
another transfer option exists that provides incremental transfer
benefits beyond PIO. Direct Memory Access (DMA) is based on data
transfer directly to memory rather than via the CPU. DMA transfers
are "throttled" and therefore have historically offered the benefit
of maximizing data throughput. The throttling mechanism associated
with DMA has historically enabled improved data transfers relative to
standard PIO.

Type B DMA was defined with the arrival of Extended Industry Standard
Architecture (EISA), and is specified at 4.0MB/sec transfer rates
offering an advantage to the standard 2-3MB/sec PIO data rates.
Although this is an improvement to the standard ISA bus timings, Type
B DMA remains uncompetitive with FAST SCSI timings of 10MB/sec.

With the advent of local bus solutions, a new DMA transfer has
emerged in conjuction with PCI. Type F DMA is defined to support
8.33MB/sec and 6.67MB/sec data rates, a large improvement over Type B
DMA. In conjunction with chipsets capable of supporting 6.67MB and
8.33MB/sec data rates, the Small Form Factor Committee has approved a
new multiword DMA Mode 1 timing specification of a 150ns cycle time.
This enables DMA transfers up to 13MB/sec for future data rate
improvement by allowing multiple words to be transferred for any
given request command. PCI chip sets will be shipping with both EISA
(Type B) and ISA (Type F) configurations in the calendar CYQ4'1993
time frame.

PIO versus DMA:
The disadvantage of DMA transfer operations is that the PC/AT hard
disk controller and later IDE, evolved around PIO data transfers.
Therefore, the system Int 13h BIOS and the embedded operating system
device drivers have supported PIO transfers versus DMA transfers.
This simply means that BIOS changes and external device drivers are
necessary to achieve the incremental performance that DMA offers.

Western Digital's Enhanced IDE program supports system manufacturers'
choice of either PIO transfers via Flow control with IORDY for Mode 3
PIO data rates or DMA transfers (both Type B and Type F) via the
development of external DMA device drivers supporting Western Digital
hard disk drives. Product platforms based on both high speed transfer
options will be in production in calendar fourth quarter 1993.

Supporting Multiple IDE Devices:
The original IBM PC/AT defined support for two hard disk controllers
and allowed support for up to four disk drives via a primary and
secondary controller. The original BIOS and operating system drivers,
however, only supported the primary controller, limiting the standard
PC configuration to two disk drives. Today's operating systems now
offer both primary and secondary controller support providing an
opportunity to extend peripheral attachment capabilities with IDE.
The addition of a second connector via a hardware change is a simple,
low cost solution that allows for multiple IDE peripheral

The cost of a second IDE connector is less than $1.00. Most core
logic and Super I/O devices have already integrated the capability to
support either the primary or secondary address decode logic and
therefore the cost of the secondary port is simply the 40 pin
connector and surrounding transceivers and resistors. For $1.00, dual
IDE connectors offer support for four IDE devices and satisfy the
expansion needs of the majority of the mainstream personal computer
market, a very cost effective alternative to connectivity via SCSI.

Western Digital's Enhanced IDE program works with system
manufacturers to understand the BIOS implications of a secondary
channel for support of two additional IDE devices. The BIOS must be
able to determine the physical location of the drive based on the Int
13h drive number . Since DOS 3.0 and later will support up to seven
disk drives, only the system BIOS Interrupt 13h needs to be modified
to support primary and secondary IDE. Windows 3.1 accesses the disk
via Interrupt 13h calls to the BIOS. Again, all that is required is
modification to the system BIOS to support dual channel IDE. IBM OS/2
2.0 and 2.1 as well as MS/IBM OS/2 1.31 all support four IDE drives
on dual IDE connectors via their drivers. Netware is hardcoded to
support four IDE connectors or 8 IDE devices. Dual channel IDE
support will be in the final release of Windows NT.

Dual channel IDE not only enables the cost effective and easy
implementation to support multiple disk drives, it presents the
opportunity to expand IDE into non-disk peripheral support. A slow
speed channel and a high speed channel can be developed for efficient
implementation of storage solutions via high performance hard disk
drives and mass data storage vehicles such as CD-ROM and tape drives.

Enabling Non-disk Peripheral Connectivity:
The upcoming high performance desktop machines are demanding
additional storage peripheral support beyond hard disk drives.
Specifically, CD-ROM and tape drives will demonstrate rapid unit
growth rates as these peripherals become a more standard part of the
desktop's configuration. Today's CD- ROMs and tape drives have
multiple interfaces that present compatibility and performance
issues. Development of a standard IDE interface for both CD-ROMs and
tape drives solves cost, compatibility, performance, and ease-of-use
issues in conjunction with enabling the attachment of non-disk
devices via the IDE interface.

Western Digital, with its AT interface expertise, has taken the
leadership position in expanding the IDE interface to support
non-disk peripherals by authoring the AT Attachment Packet Interface
(ATAPI). The specification defines a standard method for interfacing
to a CD-ROM drive (and other non-disk devices) utilizing the existing
ATA host computer hardware and cabling. ATAPI supplements the
definitions of an ATA mass storage peripheral found in the ATA
specification and is compatible with existing ATA hardware without
any changes or additional pins.

Traditional computer architecture has used a register based transport
mechanism. Modern architectures now use packet-based transport
mechanisms. ATAPI is an enhancement to IDE that follows this trend.
Benefits of including a packet-based scheme means adding very few IDE
operation codes. The ATAPI specification adds only a single new IDE
command to obtain functionality and only two additional new IDE
commands to address compatibility. Once a packet-based interface was
defined, the next issue was deciding what command packets definitions
to utilize. Given widespread support for SCSI within peripherals and
within existing operating systems, it was decided to derive ATAPI
command packets from SCSI to minimize development time and expense.

The ATAPI specification is being reviewed by an industry working
group that consists of market-making system manufacturers, CD-ROM
suppliers, silicon designers, BIOS developers, and Western Digital.
The objective is to finalize the ATAPI specification around which
these companies will design and manufacture products for the personal
computer industry. Although the exact strategy has yet to be decided
upon, the document will eventually be submitted to a standards
committee for adoption.

 Putting it All Together
     Support for four IDE devices
     Fast IDE port for disk drives
     Slow IDE port for CD-ROMs and tape
     True plug and play
     Lowest cost of connection
     Overlapped I/Os for higher performance

The Big Picture:
It is clear that the mass storage needs of the personal computer
industry are expanding to include higher performance and connectivity
requirements. Enhanced IDE was developed in response to these
requirements. The industry is already embracing Enhanced IDE and its
elements of improved functionality, performance, and connectivity by
introducing products in the calendar fourth quarter of 1993. These
products include BIOS support for >528MB IDE hard disk drives, the
shipment of >528MB IDE drives themselves, silicon and controller
products supporting fast PIO and DMA transfers, and hardware
supporting dual channel IDE for multiple device connectivity.
Momentum in the development of the industry's first standard IDE non-
disk peripherals is well underway with the industry's first IDE
CD-ROMs anticipated to ship in calendar first quarter 1994.

SCSI and IDE Scorecard:
The industry activity backed by real Enhanced IDE products means that
IDE has met the challenge in addressing the industry's new
requirements. IDE's cost effectiveness and compatibility advantages,
matched now with high performance and connectivity attributes make it
a solid storage interface solution well into the future. A new
comparison of the AT/SCSI scorecard reveals the successful approach
of Enhanced IDE:

Standard AT Interface
* The IDE interface supports two disk drives.

* IDE is a hard disk only interface.

 * The IDE interface is limited to 528MB hard disk capacity as as
   result of the Int 13h BIOS interface used to access IDE drives.

 * The IDE interface is typically limited to 2-3MB/sec host

 With Enhanced IDE
 * The IDE interface supports four IDE devices with dual channel IDE
   and more with multiple IDE connectors.

 * The IDE interface supports non-disk peripherals such as IDE CD-ROM,
   IDE Tape.

 * With LBA, the IDE interface supports up to 8.4G of hard disk

 * With Mode 3 PIO and multiword DMA mode 1, data transfer rates with
   IDE drives can be from 11MB/sec up to 13MB/sec.

With Enhanced IDE, the IDE interface has become a mass storage
interface for personal computers and is no longer simply a disk drive
interface. Enhanced IDE complements SCSI in that it remains primarily
an internal interface solution with SCSI as an external interface

Western Digital is a registered trademark of Western Digital
Corporation. All marks mentioned herein belong to other companies.
PIO transfers are based on using the CPU to perform the data transfer
(Processor I/O) and is the standard transfer method supported within
all existing BIOS and all embedded operating system device drivers.
PIO implies compatibility with existing BIOS/OS and therefore does
not require added device driver support for operation.

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