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10.05. What does an ATA-2 interface do?




Description

This item is from the Yet Another Enhanced IDE/Fast-ATA/ATA-2 FAQ, by John Wehman and Peter den Haan with numerous contributions by others. (v1.92).

10.05. What does an ATA-2 interface do?

Interfaces have come a long way since the ordinary ISA IDE consisting of little more than a simple buffer. ATA-2 boards have to support at least PIO modes 0 and 3, usually support many more modes, and will have to ensure that the correct timing is used at the ATA interface for each of these modes. Since the timing specifications are quite complicated, a great deal of flexibility is necessary to implement the ATA-2 standard correctly.

                             |<------------ t0 ------------------------>|
                       __________________________________________       |
Address Valid *1 _____/                                          \________
                      |<-t1->|<----------- t2 ----------->|<-t9->|      |
                      |      |____________________________|<---t2i----->|_
DIOR-/DIOW-      ____________/                            \_____________/
                      |      |                            |      |
                      |      |                    ________|__  ->|   |<-t8
Write Data    *2 --------------------------------<___________>------------
                      |      |                   |<--t3-->|  |       |
                      |      |                          ->|t4|<-     |
                      |      |                     _______|___ ____  |
Read Data     *2 ---------------------------------<___________X____>------
                    ->|t7|<- |                    |     ->|t6 |<-  | |
                      |  | ->| tA |<-             |<-t5-->|<-t6Z-->|
                      |  |___________________________________________|
IOCS16-          ________/        |               |                  \____
                                  |             ->|tRd|<-            |
                 _________________|___________________|___________________
IORDY            XXXXXXXXXXXXXXXXX____________________/
                                  |<-------tB-------->|

*1 Device Address consists of signals CS0-, CS1- and DA2-0

*2 Data consists of DD0-15 (16-bit) or DD0-7 (8-bit)

The above figure defines the relationships between the interface signals for both 8-bit and 16-bit PIO data transfers.

In this diagram, t0 denotes the read/write cycle time, the most significant determining parameter for PIO mode throughput. As you can see, there is a lot more to the various PIO and DMA modes than this read/write cycle time only. To design a low-cost interface that fully adheres to the ATA-2 specification is quite a challenge. The common approach is to make the timing completely software programmable; unfortunately, the way ATA cards are programmed has not been standardized and differs radically between cards. The consequence is that you will typically need interface-specific drivers for each and every operating system used in order to profit from the fast transfer modes.

 

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