4.3) What does the power on self-test check?
Description
This article is from the comp.sys.acorn FAQ, by Paul Vigay with numerous contributions by others.
4.3) What does the power on self-test check?
The power on self test was introduced with RISC OS 3.0 and later versions of the OS. On power up your machine checks the hardware for physical faults before letting you use it, hopefully signalling important errors to you before further hardware damage can result.
The purple screen at power on indicates that the self-test has begun. A brief ROM, RAM, VIDC and IOC test is performed and then the screen colour changes to blue and a limited memory test [1] is performed, along with a second test of the VIDC and IOC. When the screen returns to purple, the machine is testing for an ARM3 (or better). At the end of this sequence the screen colour is set to green (for pass) or red (for fail). If the tests have all passed then the machine starts to boot and the RISC OS 3 welco me screen is displayed.
If any test fails, the screen will remain red and the disc drive light will blink a fault code. A short flash is used to indicate a binary '0' and a long flash indicates a binary '1'. The bits are grouped into eight nybbles (blocks of four bits) with the most significant bit first.
The lowest seven bits are a status word. The meaning of each bit is given below in hex :-
00000001 Self-test due to power on 00000002 Self-test due to interface hardware 00000004 Self-test due to test link 00000008 Long memory test performed 00000010 ARM ID detected (ARM 3 fitted for non-RiscPC hardware) 00000020 Long memory test disabled 00000040 PC-style IO world detected 00000080 VRAM detected
Bits 8-31 indicate the fault code and are described below. Not all the bits are used. If the code is marked as reserved on the RiscPC this means that error number is currently either unassigned or it's meaning on older hardware is no longer sensible for the newer machines (and thus it's meaning may be reassigned on the newer versions of the OS.)
00000100 CMOS RAM checksum error 00000200 ROM failed checksum test 00000400 MEMC CAM mapping failed (A reserved code on the RiscPC) 00000800 MEMC protection failed (A reserved code on the RiscPC) 00001000 (A reserved code on the RiscPC) 00002000 (A reserved code on the RiscPC) 00004000 VIDC Virq (video interrupt) timing failed 00008000 VIDC Sirq (sound interrupt) timing failed 00010000 CMOS unreadable 00020000 RAM control line failure 00040000 Long RAM test failure 00080000 (A reserved code on the RiscPC)
Some third party VIDC enhancers on older hardware trigger the self test to fail. If you are getting a failed self test with a VIDC enhancer, yet the machine is working fine, enter and run this BASIC program and then save your CMOS settings:-
REM Toggle state of power on self test bit in CMOS REM Read byte SYS "OS_Byte",161,&BC TO ,,byte% REM EOR byte with mask for bit 1 byte% = byte% EOR %10000000 REM Write byte back again SYS "OS_Byte",162,&BC,byte% END
This modifies the self test to cope with the VIDC enhancer.
[1] By limited it meant that it verifies the VRAM, if present, and checks the first 4 MB of RAM in the machine. (Or so I am told.)
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