GIGA-BYTE TECHNOLOGY CO., LTD.
GA-386ES (25/33)
Processor | 80386DX |
Processor Speed | 25/33MHz |
Chip Set | Elite |
Max. Onboard DRAM | 32MB |
Cache | 64/128KB |
BIOS | AMI |
Dimensions | 330mm x 218mm |
I/O Options | 32-bit external memory card slot |
NPU Options | 80387/3167 |
CONNECTIONS | |||
Purpose | Location | Purpose | Location |
External battery | J4 | Power LED & keylock | J41 |
Turbo LED | J34 | Speaker | J42 |
Turbo switch | J39 | 32-bit external memory card | S1 |
Reset switch | J40 |
USER CONFIGURABLE SETTINGS | |||
Function | Jumper | Position | |
» | CMOS memory normal operation (internal battery) | J3 | Closed |
CMOS memory normal operation (external battery at J4) | J3 | Open | |
CMOS memory clear (no external battery at J4) | J3 | Open | |
» | Monitor type select color | J17 | Closed |
Monitor type select monochrome | J17 | Open |
DRAM CONFIGURATION | ||
Size | Bank 0 | Bank 1 |
1MB | (4) 256K x 9 | NONE |
2MB | (4) 256K x 9 | (4) 256K x 9 |
4MB | (4) 1M x 9 | NONE |
5MB | (4) 1M x 9 | (4) 256K x 9 |
8MB | (4) 1M x 9 | (4) 1M x 9 |
16MB | (4) 4M x 9 | NONE |
17MB | (4) 4M x 9 | (4) 256K x 9 |
20MB | (4) 4M x 9 | (4) 1M x 9 |
32MB | (4) 4M x 9 | (4) 4M x 9 |
CACHE CONFIGURATION | ||||
Size | Bank 0 | Bank 1 | J32 | J33 |
64KB (A) | (8) 8K x 8 | NONE | pins 1 & 2 closed | pins 1 & 2 closed |
64KB (B) | (4) 8K x 8 | (4) 8K x 8 | pins 1 & 2 closed | pins 1 & 2 closed |
128KB (A) | (8) 8K x 8 | (8) 8K x 8 | pins 2 & 3 closed | pins 2 & 3 closed |
128KB (B) | (4) 32K x 8 | NONE | pins 2 & 3 closed | pins 2 & 3 closed |
Note:On mainboards installed with 16 CACHE sockets, use (A) settings, on mainboards installed with 8 CACHE sockets use (B) settings. |
CACHE JUMPER CONFIGURATION | ||
Size | J32 | J33 |
64KB (A) | pins 1 & 2 closed | pins 1 & 2 closed |
64KB (B) | pins 1 & 2 closed | pins 1 & 2 closed |
128KB (A) | pins 2 & 3 closed | pins 2 & 3 closed |
128KB (B) | pins 2 & 3 closed | pins 2 & 3 closed |
Note:On mainboards installed with 16 CACHE sockets, use (A) settings, on mainboards installed with 8 CACHE sockets use (B) settings. |